The cornerstone of modern analog/RF circuit design is the accuracy of foundry supplied device models. Using these models, circuit designers are able to apply monte-carlo methods to determine a statistical range over which their fabricated designs will operate, and then optimize their circuit designs such that the achieved performance lies within a set of acceptable bounds. In order for this approach to be successful, the foundry models must be accurate enough to predict the performance of the fabricated chips. For mature technologies, designers can rely on corner and monte-carlo models to provide accurate information. However, in emerging technologies, such as state-of-the-art nm CMOS, the RF models are not sufficiently developed, and the measured performance may lie significantly outside the distribution predicted using monte-carlo simulations. For example, due to the incomplete nature of noise models associated with nanometer scale CMOS devices, the performance of low-noise amplifiers (LNAs) fabricated in these technologies can be significantly worse than predicted by simulation. Thus, an alternative design approach that does not rely upon the accuracy of device models is required in order to take full advantage of these emerging technology platforms. In this work, we are developing new techniques which will allow designers to implement state-of-the-art low noise circuits without the need for extremely accurate device models.