Over the past fourty years, we have seen the performance of computers improve exponentially as the feature size in CMOS processors has been reduced. While todays state-of-the-art CMOS transistors—with features of just 22nm—enable the realization of complex digital functions at blazing speeds, their efficiency is fundamentally limited by the signal swings, which must be greater than a thermal voltage. An alternative technology is superconducting logic, which is intrinically hundreds of times more efficient than its silicon counterpart and can be operated at speeds above 750 GHz. Unfortunately, superconducting logic must be cooled to liquid helium temperatures in order to function. Moreover, as the signal swings are quite small, cold amplification is required to interface to room temperature electronics. As the power requirements for the cooling system scale with the power dissipation of the cryogenic electronics, this amplification can dominate the power budget of the superconducting computer.

In this work, we are attacking the problem of getting the signal out of the cryostat while keeping the power dissipation to a minimum. To acomplish this goal, we are designing a custom silicon germanium chipset that will be optimally distributed along the thermal transition from 4 K to room temperature. The design and optimization of this link is enabled by custom device models that are able to predict the noise and transient perforamnce of complex integrated circuits at these low temperatures.